This book provides detailed information on the interconnect RC and layut extraction in integrated circuit chips. The RC and layout extraction is a part of the job in the physical design and timing analysis for high-speed circuit design. The accuracy of interconnects RC model as well as the extracted device sizes from the physical layout are critical to the timing analysis result and circuit performance. Due to the complexity of the millions of gates and interconnects in VLSI chis, theRC and layout extraction is accomplished using CAD tools. This sort of tool takes the layout database usually in GDSII files and extracts the RC parasite and device sizes in the layout. The results are usually written to standard netlist formats. In addition, the extracted netlist is back annotated to the interconnects andphysical transistor sizes.

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