VLSI planarization is one of the basic stages of the so-called topological approach to VLSI design. This book considers the intense recent development in this field. Although it features an analysis of the problem and the results of different authors are classified and generalized, this volume is mainly based on the investigations conducted by the present authors during the last fifteen years. This included work in the field of design and research in mathematical methods applied to the mentioned approach for computer-aided design, and in the field of designing concrete industrial design systems. The theory and methods discussed here may be applied to printed-circuit boards, hybrid circuits, etc. This work concentrates on `essentially' hypergraph models of electric circuits and their planarization techniques. It is just this aspect of the topological approach to design that has not been adequately investigated before. Audience: This book will be of interest to theoretical and applied mathematicians whose work involves VLSI design, algorithms, graph theory and complexity theory, and EDA tools developers.