The work presented in Power Trade-offs and Low Power in Analog CMOS ICs concerns power, noise and accuracy in CMOS Analog IC Design. In the presented material it is shown that power, noise and accuracy should be treated in an unitary way, the three terms being well inter-related. The book is divided in a theoretical part which covers sub-micron digital and sub-micron analog followed by an applicative part where accuracy related power and noise related power is encountered. The main part of the book deals with analog circuits working in a digital environment where the process has been optimized for digital applications. The general trend, in digital, to scale down the power supply makes the process of designing analog circuits a difficult task since most of the solutions valid for large supply voltages are not anymore useful due to the low voltage limitations. At low supply voltage, the key problem of analog signal processing functions is dynamic range reduction. In all cases this yields in an increase of power consumption. Besides, analog designers have to cope with second order effects generated by the incompatibility of the process with analog performance. To get the best performance, knowing the limits of power in analog circuits and clearly defining the environment where analog circuits should work is a must. Starting from fundamental/physical limits we are discussing the practical limits of power in digital, mostly at the architecture level and practical limits of power in analog at circuit and architecture level. The fundamental limits are asymptotic limits and they cannot provide realistic comparisons between possible solutions. That is why the approach here provides a step further into power analysis by discussing all possible practical specs related to power at circuit and architecture level. For analog circuits Dynamic-Range*Speed product is limited by power, topology and supply voltage regardless of the type of circuits: continuous time or sampled data, current-mode or voltage mode.