The Second Edition of Writing Testbenches, Functional Verification of HDL Models presents the latest verification techniques to produce fully functional first silicon ASICs, systems-on-a-chip (SoC), boards and entire systems.

From the Foreword: Building on the first edition, " ...the most successful and popular contemporary verification textbook", the author raises the verification level of abstraction by introducing coverage-driven constrained random transaction-level self-checking testbenches - all made possible through the introduction of hardware verification languages (HVLs) such as e from Verisity and OpenVera from Synopsys...." Harry Foster, Chief Architect, Verplex Systems, Inc. Topics included in the new Second Edition: + Discussions on OpenVera and e; + approaches for writing constrainable random stimulus generators; + strategies for making testbenches self-checking; + a clear blueprint of a verification process that aims for first time success; + recent advances in functional verification such as coverage-driven verification process; + VHDL and Verilog language semantics; + the semantics are presented in new verification-oriented languages + techniques for applying stimulus and monitoring the response of a design; + behavioral modeling using non-synthesizeable constructs and coding style; + updated for Verilog 2001.

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