Aimed at the goal of true single-chip wireless devices, this book provides analyses of challenges involved with the co-integration of active and passive devices in RFIC design, and how modeling parasitic properties during the design phase can minimize undesirable effects such as the de-tuning of RF circuits. The book begins with background on "parasitic-aware" optimization, and then covers topics including monolithic inductors; simulated annealing with tunneling process; particle swarm optimization; and optimization of CMOS low-noise amps, mixers, RF power amps, and CMOS ultra-wideband amps.